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    <title>The Tech Gazette · Papers · Systems and databases</title>
    <link>https://techgazette.com.br/research/#systems</link>
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    <description>This week's papers in Systems and databases, each with what its authors did and found, in sentences from its own abstract.</description>
    <language>en</language>
    <ttl>180</ttl>
    <lastBuildDate>Sat, 17 Oct 2026 12:00:00 GMT</lastBuildDate>
    <item>
      <title>AdaFuse: Adaptive Function Fusion for Dynamic Serverless Workflows</title>
      <link>https://dl.acm.org/doi/10.1145/3859287</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3859287</guid>
      <pubDate>Sat, 17 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization) — Did: Serverless workflows are commonly modeled as directed acyclic graphs (DAGs) composed of fine-grained functions.</description>
    </item>
    <item>
      <title>TraHist: Fast and Accurate Cardinality Estimation for Trajectory Data (Extended Version)</title>
      <link>https://arxiv.org/abs/2610.22310</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.22310</guid>
      <pubDate>Thu, 15 Oct 2026 17:50:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DB</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DB — Did: To this end, we propose TraHist, a histogram-based estimator approximating density-aligned partitioning via efficient grid-based propagation. Found: Experiments on large-scale real-world datasets show that TraHist reduces estimation error by over 20x relative to the strongest competing estimator in query regimes where trajectory fragmentation is a dominant source of estimation error, while maintaining sub-millisecond query latency and competitive construction cost. By Yujeong Jo, Incheol Baek, Changbeom Shim, Yon Dohn Chung.</description>
    </item>
    <item>
      <title>Architecting for Hardware Diversity: Meta's End-to-End Co-Design for High-Performance AI Training on AMD GPUs</title>
      <link>https://arxiv.org/abs/2610.22230</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.22230</guid>
      <pubDate>Thu, 15 Oct 2026 17:09:00 GMT</pubDate>
      <dc:creator>arXiv cs.DC</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv cs.DC — Did: This paper presents our methods for optimizing alternative accelerators, using AMD Instinct MI350X versus NVIDIA B200 for recommendation model training as a case study. Found: Compared to the directly ported baseline, these methods deliver up to 1.5x improvement in end-to-end training throughput. By Haoyu Zhang, Arshad Rahman, Adnan Aziz, Ajith Prabhudev, Amin Farmahini, Ben Rhoads.</description>
    </item>
    <item>
      <title>Efficient KV Cache Migration for Geo-Distributed LLM Inference in Collaborative Edge Computing</title>
      <link>https://arxiv.org/abs/2610.22172</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.22172</guid>
      <pubDate>Thu, 15 Oct 2026 16:31:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DC</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DC — Did: In this work, we propose EdgeFlow, a novel hybrid KV cache migration scheme that integrates direct KV cache transmission with activation-based recomputation, leveraging parallel computation and communication to minimize migration time. Found: Extensive experiments on a real-world distributed LLM inference platform demonstrate that EdgeFlow reduces migration time by up to 45%, significantly enhancing the robustness and efficiency of distributed LLM inference in collaborative edge computing. By Mingjin Zhang, Jiannong Cao, Tao Wu, Xiangchun Chen, Ne Wang.</description>
    </item>
    <item>
      <title>ETH: Data-Balanced Heterogeneous Pipeline Parallelism for Training Large Models</title>
      <link>https://arxiv.org/abs/2610.22035</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.22035</guid>
      <pubDate>Thu, 15 Oct 2026 15:10:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DC</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DC — Did: In this paper, we propose Heterogeneous Pipeline Parallelism (HPP), a novel approach enabling efficient and fine-grained data balance across heterogeneous pipelines. Found: Evaluations demonstrate ETH achieves up to 2x training speedup while reducing configuration generation overhead by up to 56x compared to state-of-the-art systems. By Mianjie Yu, Zhongmin Zhao, Zizhao Mo, Jianxiong Liao, Wenxuan Li, Yulin Qiao.</description>
    </item>
    <item>
      <title>Resource-aware Sub-network Allocation for Heterogeneous Decentralized Learning</title>
      <link>https://arxiv.org/abs/2610.22015</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.22015</guid>
      <pubDate>Thu, 15 Oct 2026 14:56:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DC</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DC — Did: We propose RASA-DL, a resource-aware sub-network allocation framework that treats the maximum sub-network width assigned to each node as a deployment variable. Found: Under the Moderate and Severe regimes, the minimum-latency operating point improves accuracy over the largest globally feasible uniform deployment by 2.80 and 2.43 percentage points, respectively, at the same modeled round latency. By Zhuojun Tian, Ming Xiao, Mikael Skoglund.</description>
    </item>
    <item>
      <title>Exact Makespan Bounds and the GPipe Homogeneity Bias for Heterogeneous LLM Inference Pipelines</title>
      <link>https://arxiv.org/abs/2610.21815</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.21815</guid>
      <pubDate>Thu, 15 Oct 2026 13:03:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DC</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DC — Did: We give an exact critical-path characterization of the makespan of micro-batch pipelines serving LLMs on heterogeneous GPU clusters, quantifying how the classic homogeneous GPipe formula errs. Found: These results quantify the GPipe overestimate, decompose the bias into a homogeneity term Sum_j (tau_max - tau_j) and a communication-ignoring term Sum_j d_j, and imply that balancing per-stage compute dominates communication reduction for steady-state throughput. By Zhu Wenbo.</description>
    </item>
    <item>
      <title>Reflective Compositional Grounding for Natural-Language-to-SPARQL</title>
      <link>https://arxiv.org/abs/2610.21796</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.21796</guid>
      <pubDate>Thu, 15 Oct 2026 12:47:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DB</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DB — Did: We present an NL2SPARQL framework that places conceptual compositionality at the center of query interpretation and connects it to the relational composition required for binding and query construction. By Isabelle Mohr, John Dujany, Andre Freitas.</description>
    </item>
    <item>
      <title>Fast Forgiving Base64 Decoding with SIMD Instructions</title>
      <link>https://dl.acm.org/doi/10.1145/3859286</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3859286</guid>
      <pubDate>Thu, 15 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization) — Did: On the Internet, we use the Base64 format to represent binary data (e.g., images or cryptographic keys) as text.</description>
    </item>
    <item>
      <title>LOAD: Enabling Low-Bit Group Quantization for Vision Transformers via Adaptive Data Formats</title>
      <link>https://dl.acm.org/doi/10.1145/3857350</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3857350</guid>
      <pubDate>Thu, 15 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization) — Found: Vision Transformers (ViTs) achieve state-of-the-art performance across various vision tasks but pose significant deployment challenges due to their high computational complexity and memory footprint.</description>
    </item>
    <item>
      <title>ConStore: Search-Overlapped Prefetch and Co-Retrieval-Aware Content Storage for Disk-Based ANNS</title>
      <link>https://arxiv.org/abs/2610.21676</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.21676</guid>
      <pubDate>Thu, 15 Oct 2026 11:01:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DB</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DB — Did: We present ConStore, a content storage engine combining two complementary techniques to reduce end-to-end retrieval latency. Found: Separate experiments on 100M- and billion-vector indexes demonstrate SICP's applicability at larger scales. By Zhutao Zhuang, Nong Xiao, Zhiguang Chen, Yue Yu.</description>
    </item>
    <item>
      <title>When the KV Cache Is Slower Than the GPU: Scaling Remote KV Tiers for Context-Parallel Prefill</title>
      <link>https://arxiv.org/abs/2610.21500</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.21500</guid>
      <pubDate>Thu, 15 Oct 2026 08:37:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DC</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DC — Did: We study such a tier in a disaggregated deployment of GLM-5.3, an FP8 mixture-of-experts model with multi-head latent attention (MLA), on 8xB300 nodes running prefill context parallelism (PCP8). Found: The sharded store raises prefill throughput by 14%, and by 34% together with an upstream kernel fix. By Muhammad Ibrahim.</description>
    </item>
    <item>
      <title>AdaBool: Sparse Boolean Matrix Processing with Adaptive Data Representation</title>
      <link>https://arxiv.org/abs/2610.21264</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.21264</guid>
      <pubDate>Thu, 15 Oct 2026 05:00:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.DB</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.DB — Did: We present AdaBool, a SpBMM framework designed to reconcile this tension through an adaptive data representation. Found: We implement AdaBool end to end with low-level system optimizations, evaluate it on both production and public workloads, and show that it outperforms representative baselines by over an order of magnitude. By Xiangrui Yang, Yifan Lei, Jiawei Yang, Yekang Zhan, Yuxin Zheng, Lei Mao.</description>
    </item>
    <item>
      <title>Characterizing Predictability-Latency Trade-offs of KV-Cache SSD Offloading in LMCache for LLM Serving Systems</title>
      <link>https://arxiv.org/abs/2610.21249</link>
      <guid isPermaLink="true">https://arxiv.org/abs/2610.21249</guid>
      <pubDate>Thu, 15 Oct 2026 04:44:00 GMT</pubDate>
      <dc:creator>arXiv (systems &amp; security) cs.OS</dc:creator>
      <category>Systems and databases</category>
      <description>arXiv (systems &amp; security) cs.OS — Did: In this paper, we study LMCache through realworld multi-session workloads that span same/different context x same/different prompt, using over 100 stateless requests per workload. Found: Second, deduplication delivers a dramatic write reduction only for the exact-repeat workload: one set collapses from 1.62 GB to 11.75 MB of writes, while the other three sets remain in the 2-5 GB range. By Ying He, Dingsen Shi, Yanbo Dai, Donger Chen, Harry Fu, Chris Tsu.</description>
    </item>
    <item>
      <title>PRIOR-I/O: Real-time Performance Improvement through Dynamic Resource Allocation for Virtual I/O</title>
      <link>https://dl.acm.org/doi/10.1145/3848127</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3848127</guid>
      <pubDate>Wed, 14 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization)</description>
    </item>
    <item>
      <title>Q-GMRES: Quantized Data Transmission Optimization for Distributed GMRES Algorithm</title>
      <link>https://dl.acm.org/doi/10.1145/3857806</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3857806</guid>
      <pubDate>Wed, 14 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization) — Did: The generalized minimal residual (GMRES) algorithm is one of the key iterative algorithms for solving large-scale sparse linear systems, which finds extensive application in scientific and engineering computations.</description>
    </item>
    <item>
      <title>ReHGNN: A Digital-Analog Processing-in-Memory Architecture for Sparse-Dense Matrix Multiplication in Hypergraph Neural Networks</title>
      <link>https://dl.acm.org/doi/10.1145/3858418</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3858418</guid>
      <pubDate>Wed, 14 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization) — Did: Resistive random access memory (ReRAM) based analog processing-in-memory (APIM) architectures have been extensively explored for accelerating matrix multiplication in various artificial neural networks (ANNs).</description>
    </item>
    <item>
      <title>StrataJ: Enhancing File System Journaling Scalability via Adaptive Concurrency Control and Full-Stack Optimizations</title>
      <link>https://dl.acm.org/doi/10.1145/3858621</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3858621</guid>
      <pubDate>Wed, 14 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization) — Did: The scalability of file system journaling faces significant challenges due to the increasing concurrency demands of modern multi-core CPUs and high throughput NVMe SSDs.</description>
    </item>
    <item>
      <title>GPU-Accelerated Gate-Level Time-Based Power Analysis via Event-Density-Aware Partitioning and Kernel Fusion</title>
      <link>https://dl.acm.org/doi/10.1145/3847118</link>
      <guid isPermaLink="true">https://dl.acm.org/doi/10.1145/3847118</guid>
      <pubDate>Tue, 13 Oct 2026 12:00:00 GMT</pubDate>
      <dc:creator>ACM TACO (Architecture and Code Optimization)</dc:creator>
      <category>Systems and databases</category>
      <description>ACM TACO (Architecture and Code Optimization) — Did: Power analysis is crucial in modern chip design flow.</description>
    </item>
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